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UC2909 UC3909
Switchmode Lead-Acid Battery Charger
FEATURES
* Accurate and Efficient Control of Battery Charging * Average Current Mode Control from Trickle to Overcharge * Resistor Programmable Charge Currents * Thermistor Interface Tracks Battery Requirements Over Temperature * Output Status Bits Report on Four Internal Charge States * Undervoltage Lockout Monitors VCC and VREF
DESCRIPTION
The UC3909 family of Switchmode Lead-Acid Battery Chargers accurately controls lead acid battery charging with a highly efficient average current mode control loop. This chip combines charge state logic with average current PWM control circuitry. Charge state logic commands current or voltage control depending on the charge state. The chip includes undervoltage lockout circuitry to insure sufficient supply voltage is present before output switching starts. Additional circuit blocks include a differential current sense amplifier, a 1.5% voltage reference, a -3.9mV/C thermistor linearization circuit, voltage and current error amplifiers, a PWM oscillator, a PWM comparator, a PWM latch, charge state decode bits, and a 100mA open collector output driver.
BLOCK DIAGRAM
Pin numbers refer to J, N, DW packages.
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UDG-95007-1
1/99
UC2909 UC3909
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC), OUT, STAT0, STAT1 . . . . . . . . . . . 40V Output Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A CS+, CS- . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 to VCC (Note 1) Remaining Pin Voltages. . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C
All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Note 1: Voltages more negative than -0.4V can be tolerated if current is limited to 50mA.
CONNECTION DIAGRAMS
DIL-20, (Top View) J or N, DW Packages LCC-28, PLCC-28 (Top View) L, Q Packages
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = -40C to +85C for UC2909; 0C to +70C for UC3909; CT = 330pF, RSET = 11.5k, R10 = 10k, RTHM = 10k, VCC = 15V, Output no load, RSTAT0 = RSTAT1 = 10k, CHGENB = OVCTAP = VLOGIC, TA = TJ.
PARAMETER Current Sense AMP (CSA) Section DC Gain VOFFSET (VCSO - VCAO) CMRR VOL VOH Output Source Current Output Sink Current 3dB Bandwidth TEST CONDITIONS VID = CS+ - CS- CS- = 0, CS+ = -50mV; CS+ = -250mV CS+ = 0, CS- = 50mV; CS-- = 250mV CS+ = CS- = 2.3V, CAO = CA- VCM = -0.25 to VCC - 2, 8.8 < VCC < 14 VCM = -0.25 to VCC, 14 < VCC < 35 VID = -550mV, -0.25V < VCM < VCC-2, IO = 500A VID = +700mV, -0.25V < VCM < VCC-2, IO = -250A VID = +700mV, CSO = 4V VID = -550mV, CSO = 1V VID = 90mV, VCM = 0V 3 200 5.2 50 50 0.3 5.7 -1 4.5 0.6 6.2 -0.5 4.90 4.90 5 5 5.10 5.10 15 V/V V/V mV dB dB V V mA mA kHz MIN TYP MAX UNITS
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UC2909 UC3909
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = -40C to +85C for UC2909; 0C to +70C for UC3909; CT = 330pF, RSET = 11.5k, R10 = 10k, RTHM = 10k, VCC = 15V, Output no load, RSTAT0 = RSTAT1 = 10k, CHGENB = OVCTAP = VLOGIC, TA = TJ.
PARAMETER Current Error Amplifier (CEA) Section IB VIO (Note 2) AVO GBW VOL VOH Output Source Current Output Sink Current ICA-, ITRCK_CONTROL Voltage Amplifier (CEA) Section IB VIO (Note 2) AVO GBW VOL VOH Output Source Current Output Sink Current VAO Leakage: High Impedance State Pulse Width Modulator Section Maximum Duty Cycle Modulator Gain OSC Peak OSC Valley Oscillator Section Frequency Thermistor Derived Reference Section Initial Accuracy, VAO (RTHM = 10k) 8.8V < VCC < 35V VID = VRTHM - VR10 VID = 0, R10 = RTHM =10k (Note 3) VID = 0, R10 = RTHM =10k, -40C TA < 0C (Note 3) Line Regulation VAO VCC = 8.8V to 35V RTHM = 138k, R10 = 10k RTHM = 138k, R10 = 10k, -40C TA < 0C RTHM = 33.63k, R10 = 10k RTHM = 33.63k, R10 = 10k, -40C TA < 0C RTHM = 1.014k, R10 = 10k RTHM = 1.014k, R10 = 10k, -40C TA < 0C Charge Enable Comparator Section (CEC) Threshold Voltage Input Bias Current As a function of VA- CHGENB = 2.3V 0.99 -0.5 1 -0.1 1.01 V/V A 2.458 2.445 2.362 2.350 2.035 2.025 2.2655 2.254 2.3 2.3 3 2.495 2.495 2.398 2.398 2.066 2.066 2.3345 2.346 10 2.532 2.545 2.434 2.446 2.097 2.107 V V mV V V V V V V 198 220 242 kHz CAO = 0.6V CAO = 2.5V, 3.2V 90 63 95 71 3 1 100 80 % %/V V V Total Bias Current; Regulating Level 8.8V < VCC < 35V, VCM = 2.3V, VAO = VA- 1V < CAO < 4V TJ = 25C, F = 100kHz IO = 500A IO = -500A CAO = 4V CAO = 1V VCHGENB = GND, STAT0 = 0 & STAT1 = 0, VAO = 2.3V 4.75 -2 2 -1 60 0.25 0.1 1.2 90 0.5 0.4 5 -1 2.5 1 0.6 5.25 1 A mV dB MHz V V mA mA A 8.8V < VCC < 35V, VCHGENB = VLOGIC 8.8V < VCC < 35V, CAO = CA- 1V < VAO < 4V TJ = 25C, F = 100kHz IO = 250A IO = -5mA CAO = 4V CAO = 1V VCHGENB = GND 2 8.5 4.5 60 1 90 1.5 0.4 5 -25 3 10 11.5 -12 0.6 0.1 0.8 10 A mV dB MHz V V mA mA A TEST CONDITIONS MIN TYP MAX UNITS
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UC2909 UC3909
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = -40C to +85C for UC2909; 0C to +70C for UC3909; CT = 330pF, RSET = 11.5k, R10 = 10k, RTHM = 10k, VCC = 15V, Output no load, RSTAT0 = RSTAT1 = 10k, CHGENB = OVCTAP = VLOGIC, TA = TJ.
PARAMETER Voltage Sense Comparator Section (VSC) Threshold Voltage STAT0 = 0, STAT1 = 0, Function of VREF STAT0 = 1, STAT1 = 0, Function of VREF Over Charge Taper Current Comparator Section (OCTIC) Threshold Voltage Input Bias Current Logic 5V Reference Section (VLOGIC) VLOGIC Line Regulation Load Regulation Reference Comparator Turn-on Threshold Short Circuit Current Output Stage Section ISINK Continuous IPEAK VOL Leakage Current Maximum Sink Current Saturation Voltage Leakage Current STATLV Open Collector Outputs Section Maximum Sink Current Saturation Voltage Leakage current UVLO Section Turn-on Threshold Hysteresis ICC Section ICC (run) ICC (off) (See Fig. 1) VCC = 6.5V 13 2 19 mA mA 6.8 100 7.8 300 8.8 500 V mV VOUT = 5V IOUT = 2mA VOUT = 5V 2.5 5 0.1 0.45 3 mA V A IO=50mA VOUT=35V VOUT = 8.8V IOUT = 5mA VOUT = 35V 6 10 0.1 0.45 25 50 100 1 1.3 25 mA mA V A mA V A VREF = 0V 30 VCC = 15V 8.8V < VCC < 35V 0 < IO < 10mA 4.875 5.0 3 3 4.3 50 5.125 15 15 4.8 80 V mV mV V mA Function of 2.3V REF, CA- = CAO OVCTAP = 2.3V 0.99 -0.5 1 -0.1 1.01 V/V A 0.945 0.895 0.95 0.9 0.955 0.905 V/V V/V TEST CONDITIONS MIN TYP MAX UNITS
STAT0 & STAT1 Open Collector Outputs Section
Note 2: VIO is measured prior to packaging with internal probe pad. Note 3: Thermistor initial accuracy is measured and trimmed with respect to VAO; VAO = VA-.
PIN DESCRIPTIONS
CA-: The inverting input to the current error amplifier. CAO: The output of the current error amplifier which is internally clamped to approximately 4V. It is internally connected to the inverting input of the PWM comparator. CS-, CS+: The inverting and non-inverting inputs to the current sense amplifier. This amplifier has a fixed gain of five and a common-mode voltage range of from -250mV to +VCC.
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CSO: The output of the current sense amplifier which is internally clamped to approximately 5.7V. CHGENB: The input to a comparator that detects when battery voltage is low and places the charger in a trickle charge state. The charge enable comparator makes the output of the voltage error amplifier a high impedance while forcing a fixed 10A into CA- to set the trickle charge current. 4
UC2909 UC3909
PIN DESCRIPTIONS (cont.)
GND: The reference point for the internal reference, all thresholds, and the return for the remainder of the device. The output sink transistor is wired directly to this pin. OVCTAP: The overcharge current taper pin detects when the output current has tapered to the float threshold in the overcharge state. OSC: The oscillator ramp pin which has a capacitor (CT) to ground. The ramp oscillates between approximately 1.0V to 3.0V and the frequency is approximated by:
frequency =
1 1. 2 * CT * R SET
OUT: The output of the PWM driver which consists of an open collector output transistor with 100mA sink capability. R10: Input used to establish a differential voltage corresponding to the temperature of the thermistor. Connect a 10k resistor to ground from this point. RSET: A resistor to ground programs the oscillator charge current and the trickle control current for the oscillator ramp. The oscillator charge current is approximately 1.75 . R SET
Figure 1. ICC vs. temperature.
STAT1: This open collector pin is the second decode bit used to decode the charge states. STATLV: This bit is high when the charger is in the float state. VA-: The inverting input to the voltage error amplifier. VAO: The output of the voltage error amplifier. The upper output clamp voltage of this amplifier is 5V. VCC: The input voltage to the chip. The chip is operational between 7.5V and 40V and should be bypassed with a 1F capacitor. A typical ICC vs. temperature is shown in Figure 1. VLOGIC: The precision reference voltage. It should be bypassed with a 0.1F capacitor. Charge State Decode Chart STAT0 and STAT1 are open collector outputs. The output is approximately 0.2V for a logic 0.
STAT1 0 0 1 1 STAT0 0 1 0 1
The trickle control current (ITRCK_CONTROL) is approxi0115 . mately . R SET RTHM: A 10k thermistor is connected to ground and is thermally connected to the battery. The resistance will vary exponentially over temperature and its change is used to vary the internal 2.3V reference by -3.9mV/C. The recommended thermistor for this function is part number L1005-5744-103-D1, Keystone Carbon Company, St. Marys, PA. STAT0: This open collector pin is the first decode bit used to decode the charge states.
Trickle Charge Bulk Charge Over Charge Float Charge
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UC2909 UC3909
APPLICATION INFORMATION
A Block Diagram of the UC3909 is shown on the first page, while a Typical Application Circuit is shown in Figure 2. The circuit in Figure 2 requires a DC input voltage between 12V and 40V. The UC3909 uses a voltage control loop with average current limiting to precisely control the charge rate of a lead-acid battery. The small increase in complexity of average current limiting is offset by the relative simplicity of the control loop design. CONTROL LOOP Current Sense Amplifier This amplifier measures the voltage across the sense resistor RS with a fixed gain of five and an offset voltage of 2.3V. This voltage is proportional to the battery current. The most positive voltage end of RS is connected to CSensuring the correct polarity going into the PWM comparator. CSO = 2.3V when there is zero battery current. RS is chosen by dividing 350mV by the maximum allowable load current. A smaller value for RS can be chosen to reduce power dissipation. Maximum Charge Current, Ibulk, is set by knowing the maximum voltage error amplifier output, VOH = 5V, the maximum allowable drop across RS, and setting the resistors RG1 and RG2 such that; 5 * VRS 5 * VRS RG1 = = = RG 2 VLOGIC - CA - 5V - 2 .3V 5 * VRS = 1.852 * IBULK * RS 2 .7V (1) The VEA, VOH = 5V clamp saturates the voltage loop and consequently limits the charge current as stated in Equation 1. During the trickle bias state the maximum allowable charge current (ITC) is similarly determined:
ITC =
ITRICK _ CONTROL * RG1 RS * 5
(2)
ITRCK_CONTROL is the fixed control current into CA-. ITRCK_CONTROL is 10A when RSET = 11.5k. See RSET pin description for equation. Current Error Amplifier The current error amplifier (CA) compares the output of the current sense amplifier to the output of the voltage error amplifier. The output of the CA forces a PWM duty cycle which results in the correct average battery current. With integral compensation, the CA will have a very high DC current gain, resulting in effectively no average DC current error. For stability purposes, the high frequency gain of the CA must be designed such that the magnitude of the down slope of the CA output signal is less than or equal to the magnitude of the up slope of the PWM ramp. CHARGE ALGORITHM Refer to Figure 3 in UC3906 Data Sheet in the data book. A) Trickle Charge State STAT0 = STAT1 = STATLV = logic 0 When CHGNB is less than VREF (2.3V - 3.9mV/C), STATLV is forced low. This decreases the sense voltage divider ratio, forcing the battery to overcharge (VOC).
The maximum allowable drop across RS is specified to limit the maximum swing at CSO to approximately 2.0V to keep the CSO amplifier output from saturating. No charge/load current: VCSO = 2.3V, Max charge/load current: Vmax(CSO) = 2.3V-2.0V = 0.3V Voltage Error Amplifier: The voltage error amplifier (VEA) senses the battery voltage and compares it to the 2.3V - 3.9mV/C thermistor generated reference. Its output becomes the current command signal and is summed with the current sense amplifier output. A 5.0V voltage error amplifier upper clamp limits maximum load current. During the trickle charge state, the voltage amplifier output is opened (high impedance output) by the charge enable comparator. A trickle bias current is summed into the CA- input which sets the maximum trickle charge current.
VOC = (VREF ) *
(RS1 + RS 2 + RS 3 | | RS 4)
(RS 3 || RS 4)
(3)
During the trickle charge state, the output of the voltage error amplifier is high impedance. The trickle control current is directed into the CA- pin setting the maximum trickle charge current. The trickle charge current is defined in Equation 2. B) Bulk Charge State STAT1 = STATLV = logic 0, STAT0 = logic 1 As the battery charges, the UC3909 will transition from trickle to bulk charge when CHGENB becomes greater than 2.3V. The transition equation is
VT = VREF *
(RS1 + RS 2 + RS 3 || RS 4) (RS 2 + RS 3 || RS 4)
(4)
STATLV is still driven low.
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UC2909 UC3909
APPLICATION INFORMATION (cont.)
UDG-95008-1
Figure 2. Typical application circuit
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Pin numbers refer to J, N, DW packages.
UC2909 UC3909
APPLICATION INFORMATION (cont.)
During the bulk charge state, the voltage error amplifier is now operational and is commanding maximum charge current (IBULK) set by Equation 1. The voltage loop attempts to force the battery to VOC. C) Overcharge State STAT0 = STATLV = logic 0, STAT1 = logic 1 The battery voltage surpasses 95% of VOC indicating the UC3909 is in its overcharge state. During the overcharge charge state, the voltage loop becomes stable and the charge current begins to taper off. As the charge current tapers off, the voltage at CSO increases toward its null point of 2.3V. The center connection of the two resistors between CSO and VLOGIC sets the overcurrent taper threshold (OVCTAP). Knowing the desired overcharge terminate current (IOCT), the resistors ROVC1 and ROVC2 can be calculated by choosing a value of ROVC2 and using the following equation: D) Float State STAT0 = STAT1 = STATLV = logic 1 The battery charge current tapers below its OVCTAP threshold, and forces STATLV high increasing the voltage sense divider ratio. The voltage loop now forces the battery charger to regulate at its float state voltage (VF).
VF = (VREF )
(RS1 + RS 2 + RS 3 )
(6)
RS 3
If the load drains the battery to less than 90% of VF, the charger goes back to the bulk charge state, STATE 1. OFF LINE APPLICATIONS For off line charge applications, either Figure 3 or Figure 4 can be used as a baseline. Figure 3 has the advantage of high frequency operation resulting in a small isolation transformer. Figure 4 is a simpler design, but at the expense of larger magnetics.
ROVC1 = (18518 ) * IOCT * RS * ROVC 2 .
(5)
UDG-95009
Figure 3. Off line charger with primary side PWM
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UC2909 UC3909
APPLICATION INFORMATION (cont.)
UDG-95010
Figure 4. Isolated off line charger
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
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